-- ------------------------------------------------------------- -- -- Module: filter -- -- Generated by MATLAB(R) 7.1 and the Filter Design HDL Coder 1.3. -- -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- HDL Code Generation Options: -- -- TargetLanguage: VHDL -- LoopUnrolling: On -- ResetType: Sync -- InlineConfigurations: Off -- SafeZeroConcat: Off -- TestBenchStimulus: impulse step ramp chirp noise -- -- Filter Settings: -- -- Discrete-Time FIR Filter (real) -- ------------------------------- -- Filter Structure : Direct-Form FIR -- Filter Length : 16 -- Stable : Yes -- Linear Phase : Yes (Type 2) -- Arithmetic : fixed -- Numerator : s13,12 -> [-1 1) -- Input : s12,11 -> [-1 1) -- Filter Internals : Specify Precision -- Output : s16,11 -> [-16 16) -- Product : s31,31 -> [-5.000000e-001 5.000000e-001) -- Accumulator : s33,30 -> [-4 4) -- Round Mode : convergent -- Overflow Mode : wrap -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.ALL; ENTITY filter IS PORT( clk : IN std_logic; clk_enable : IN std_logic; reset : IN std_logic; filter_in : IN std_logic_vector(11 DOWNTO 0); -- sfix12_En11 filter_out : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En11 ); END filter; ---------------------------------------------------------------- --Module Architecture: filter ---------------------------------------------------------------- ARCHITECTURE rtl OF filter IS -- Local Functions -- Type Definitions TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(11 DOWNTO 0); -- sfix12_En11 -- Constants CONSTANT coeff1 : signed(12 DOWNTO 0) := to_signed(-198, 13); -- sfix13_En12 CONSTANT coeff2 : signed(12 DOWNTO 0) := to_signed(130, 13); -- sfix13_En12 CONSTANT coeff3 : signed(12 DOWNTO 0) := to_signed(272, 13); -- sfix13_En12 CONSTANT coeff4 : signed(12 DOWNTO 0) := to_signed(66, 13); -- sfix13_En12 CONSTANT coeff5 : signed(12 DOWNTO 0) := to_signed(-312, 13); -- sfix13_En12 CONSTANT coeff6 : signed(12 DOWNTO 0) := to_signed(-171, 13); -- sfix13_En12 CONSTANT coeff7 : signed(12 DOWNTO 0) := to_signed(753, 13); -- sfix13_En12 CONSTANT coeff8 : signed(12 DOWNTO 0) := to_signed(1709, 13); -- sfix13_En12 CONSTANT coeff9 : signed(12 DOWNTO 0) := to_signed(1709, 13); -- sfix13_En12 CONSTANT coeff10 : signed(12 DOWNTO 0) := to_signed(753, 13); -- sfix13_En12 CONSTANT coeff11 : signed(12 DOWNTO 0) := to_signed(-171, 13); -- sfix13_En12 CONSTANT coeff12 : signed(12 DOWNTO 0) := to_signed(-312, 13); -- sfix13_En12 CONSTANT coeff13 : signed(12 DOWNTO 0) := to_signed(66, 13); -- sfix13_En12 CONSTANT coeff14 : signed(12 DOWNTO 0) := to_signed(272, 13); -- sfix13_En12 CONSTANT coeff15 : signed(12 DOWNTO 0) := to_signed(130, 13); -- sfix13_En12 CONSTANT coeff16 : signed(12 DOWNTO 0) := to_signed(-198, 13); -- sfix13_En12 -- Signals SIGNAL delay_pipeline : delay_pipeline_type(0 TO 15); -- sfix12_En11 SIGNAL product16 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product15 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_1 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product14 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_2 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product13 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_3 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product12 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_4 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product11 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_5 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product10 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_6 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product9 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_7 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product8 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_8 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product7 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_9 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product6 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_10 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product5 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_11 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product4 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_12 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product3 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_13 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product2 : signed(30 DOWNTO 0); -- sfix31_En31 SIGNAL mul_temp_14 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL product1 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL mul_temp_15 : signed(24 DOWNTO 0); -- sfix25_En23 SIGNAL sum1 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum2 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_1 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum3 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_2 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum4 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_3 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum5 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_4 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum6 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_5 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum7 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_6 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum8 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_7 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum9 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_8 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum10 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_9 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum11 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_10 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum12 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_11 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum13 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_12 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum14 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_13 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL sum15 : signed(32 DOWNTO 0); -- sfix33_En30 SIGNAL add_temp_14 : signed(34 DOWNTO 0); -- sfix35_En31 SIGNAL output_typeconvert : signed(15 DOWNTO 0); -- sfix16_En11 SIGNAL output_register : signed(15 DOWNTO 0); -- sfix16_En11 BEGIN -- Block Statements Delay_Pipeline_process : PROCESS (clk) BEGIN IF clk'event AND clk = '1' THEN IF reset = '1' THEN delay_pipeline(0 TO 15) <= (OTHERS => (OTHERS => '0')); ELSIF clk_enable = '1' THEN delay_pipeline(0) <= signed(filter_in); delay_pipeline(1 TO 15) <= delay_pipeline(0 TO 14); END IF; END IF; END PROCESS Delay_Pipeline_process; mul_temp <= delay_pipeline(15) * coeff16; product16 <= resize( mul_temp(22 DOWNTO 0) & "00000000", 31); mul_temp_1 <= delay_pipeline(14) * coeff15; product15 <= resize( mul_temp_1(22 DOWNTO 0) & "00000000", 31); mul_temp_2 <= delay_pipeline(13) * coeff14; product14 <= resize( mul_temp_2(22 DOWNTO 0) & "00000000", 31); mul_temp_3 <= delay_pipeline(12) * coeff13; product13 <= resize( mul_temp_3(22 DOWNTO 0) & "00000000", 31); mul_temp_4 <= delay_pipeline(11) * coeff12; product12 <= resize( mul_temp_4(22 DOWNTO 0) & "00000000", 31); mul_temp_5 <= delay_pipeline(10) * coeff11; product11 <= resize( mul_temp_5(22 DOWNTO 0) & "00000000", 31); mul_temp_6 <= delay_pipeline(9) * coeff10; product10 <= resize( mul_temp_6(22 DOWNTO 0) & "00000000", 31); mul_temp_7 <= delay_pipeline(8) * coeff9; product9 <= resize( mul_temp_7(22 DOWNTO 0) & "00000000", 31); mul_temp_8 <= delay_pipeline(7) * coeff8; product8 <= resize( mul_temp_8(22 DOWNTO 0) & "00000000", 31); mul_temp_9 <= delay_pipeline(6) * coeff7; product7 <= resize( mul_temp_9(22 DOWNTO 0) & "00000000", 31); mul_temp_10 <= delay_pipeline(5) * coeff6; product6 <= resize( mul_temp_10(22 DOWNTO 0) & "00000000", 31); mul_temp_11 <= delay_pipeline(4) * coeff5; product5 <= resize( mul_temp_11(22 DOWNTO 0) & "00000000", 31); mul_temp_12 <= delay_pipeline(3) * coeff4; product4 <= resize( mul_temp_12(22 DOWNTO 0) & "00000000", 31); mul_temp_13 <= delay_pipeline(2) * coeff3; product3 <= resize( mul_temp_13(22 DOWNTO 0) & "00000000", 31); mul_temp_14 <= delay_pipeline(1) * coeff2; product2 <= resize( mul_temp_14(22 DOWNTO 0) & "00000000", 31); mul_temp_15 <= delay_pipeline(0) * coeff1; product1 <= resize( mul_temp_15(24 DOWNTO 0) & "0000000", 33); add_temp <= resize(product1 & '0', 35) + resize(product2, 35); sum1 <= resize( shift_right(add_temp(33 DOWNTO 0) + ( "0" & (add_temp(1))), 1), 33); add_temp_1 <= resize(sum1 & '0', 35) + resize(product3, 35); sum2 <= resize( shift_right(add_temp_1(33 DOWNTO 0) + ( "0" & (add_temp_1(1))), 1), 33); add_temp_2 <= resize(sum2 & '0', 35) + resize(product4, 35); sum3 <= resize( shift_right(add_temp_2(33 DOWNTO 0) + ( "0" & (add_temp_2(1))), 1), 33); add_temp_3 <= resize(sum3 & '0', 35) + resize(product5, 35); sum4 <= resize( shift_right(add_temp_3(33 DOWNTO 0) + ( "0" & (add_temp_3(1))), 1), 33); add_temp_4 <= resize(sum4 & '0', 35) + resize(product6, 35); sum5 <= resize( shift_right(add_temp_4(33 DOWNTO 0) + ( "0" & (add_temp_4(1))), 1), 33); add_temp_5 <= resize(sum5 & '0', 35) + resize(product7, 35); sum6 <= resize( shift_right(add_temp_5(33 DOWNTO 0) + ( "0" & (add_temp_5(1))), 1), 33); add_temp_6 <= resize(sum6 & '0', 35) + resize(product8, 35); sum7 <= resize( shift_right(add_temp_6(33 DOWNTO 0) + ( "0" & (add_temp_6(1))), 1), 33); add_temp_7 <= resize(sum7 & '0', 35) + resize(product9, 35); sum8 <= resize( shift_right(add_temp_7(33 DOWNTO 0) + ( "0" & (add_temp_7(1))), 1), 33); add_temp_8 <= resize(sum8 & '0', 35) + resize(product10, 35); sum9 <= resize( shift_right(add_temp_8(33 DOWNTO 0) + ( "0" & (add_temp_8(1))), 1), 33); add_temp_9 <= resize(sum9 & '0', 35) + resize(product11, 35); sum10 <= resize( shift_right(add_temp_9(33 DOWNTO 0) + ( "0" & (add_temp_9(1))), 1), 33); add_temp_10 <= resize(sum10 & '0', 35) + resize(product12, 35); sum11 <= resize( shift_right(add_temp_10(33 DOWNTO 0) + ( "0" & (add_temp_10(1))), 1), 33); add_temp_11 <= resize(sum11 & '0', 35) + resize(product13, 35); sum12 <= resize( shift_right(add_temp_11(33 DOWNTO 0) + ( "0" & (add_temp_11(1))), 1), 33); add_temp_12 <= resize(sum12 & '0', 35) + resize(product14, 35); sum13 <= resize( shift_right(add_temp_12(33 DOWNTO 0) + ( "0" & (add_temp_12(1))), 1), 33); add_temp_13 <= resize(sum13 & '0', 35) + resize(product15, 35); sum14 <= resize( shift_right(add_temp_13(33 DOWNTO 0) + ( "0" & (add_temp_13(1))), 1), 33); add_temp_14 <= resize(sum14 & '0', 35) + resize(product16, 35); sum15 <= resize( shift_right(add_temp_14(33 DOWNTO 0) + ( "0" & (add_temp_14(1))), 1), 33); output_typeconvert <= resize( shift_right(sum15(32) & sum15(32 DOWNTO 0) + ( "0" & (sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19) & NOT sum15(19))), 19), 16); Output_Register_process : PROCESS (clk) BEGIN IF clk'event AND clk = '1' THEN IF reset = '1' THEN output_register <= (OTHERS => '0'); ELSIF clk_enable = '1' THEN output_register <= output_typeconvert; END IF; END IF; END PROCESS Output_Register_process; -- Assignment Statements filter_out <= std_logic_vector(output_register); END rtl;